Matrix multiplier in GF(2{HU m{b )

摘要

The invention comprises circuitry for systematically multiplying two arbitrary field elements in a Galois field GF(2m). Each element is represented by an m-bit binary number. The multiplicand field element is passed serially through a plurality of m-1 modulo multipliers. The multiplicand and the product from each of the m-1 modulo multipliers are passed through networks which are gated by bits of the multiplier field element forming partial products. The partial products are summed to form the bit representations of the final product.