发明名称 Semiconductor device and manufacturing method thereof for protecting metal-gate from oxidation
摘要 A semiconductor device and a manufacturing method thereof is provided. The method comprises: providing a substrate for the semiconductor device with a gate structure and a first dielectric interlayer being formed thereon, said gate structure comprising a metal gate and an upper surface of said first dielectric interlayer being substantially flush with an upper surface of said gate; forming an interface layer to cover at least the upper surface of said gate such that the upper surface of said gate is protected from being oxidized; and forming a second dielectric interlayer on said interface layer.
申请公布号 US9324662(B2) 申请公布日期 2016.04.26
申请号 US201113316165 申请日期 2011.12.09
申请人 SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION 发明人 Wang Xinpeng;Huang Yi;Chang Shih-Mou
分类号 H01L21/44;H01L21/4763;H01L21/336;H01L23/00;H01L29/78;H01L21/768;H01L29/66 主分类号 H01L21/44
代理机构 Koppel, Patrick, Heybl & Philpott 代理人 Koppel, Patrick, Heybl & Philpott
主权项 1. A method of manufacturing a semiconductor device, comprising: providing a substrate for the semiconductor device with a gate structure and a first dielectric interlayer formed on the substrate and with an active area in the substrate, which is adjacent to the gate structure, wherein the first dielectric interlayer covering the active area,said gate structure comprises a metal gate andan upper surface of said first dielectric interlayer which is substantially flush with an upper surface of said metal gate; forming an interface layer on said substrate to cover the upper surface of said metal gate and the upper surface of said first dielectric interlayer; forming a second dielectric interlayer on said interface layer; etching said second dielectric interlayer to form openings that penetrate through said second dielectric interlayer, thereby exposing parts of a surface of said interface layer which respectively overlie the upper surface of said metal gate and a part of the upper surface of said first interlayer dielectric layer, wherein the etching of said second dielectric interlayer is deliberately stopped at said interface layer; and with the patterned second dielectric interlayer as a mask, etching the exposed parts of said interface layer to expose parts of the first interlayer dielectric layer and then etching the exposed parts of the first dielectric interlayer to form openings exposing at least a part of upper surface of said metal gate and at least a part of the active area.
地址 Beijing CN