| 摘要 |
<p>A multiprocessor 100 may have a plurality of chips 32 each may have a plurality of cores 11 each comprising inclusive L1, L2 caches (20, 22). Each chip may also have a shared L3 cache 24 and the system may include an L4 cache 26 and memory 34. The system provides for fetching a cache line into a plurality of caches (20 ... 26) of the multilevel inclusive cache arrangement. A fetch request is sent from one cache to the next higher level cache; the request may be a prefetch request. The requested cache line is fetched in a first state, for example a read-only state, into one of the caches and fetched in a second state, such as an exclusive state, into at least one of the other caches.</p> |
