| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock voltage doubler for stably generating a well bias voltage and supplying a stable boosted clock. SOLUTION: The clock voltage doubler uses two signals: a level shift clock signal in phase to a boosted clock and a level shift clock signal with an opposite phase thereto to produce a well bias voltage in a full wave rectification form, and supplies the produced voltage to a well of a transistor for driving the boosted clock signal. The one level shift clock signal is given to a gate of a MOS transistor and the other level shift clock signal is given to the source, and the well bias voltage is obtained from the drain. Moreover, the well bias voltage is obtained from the level shift clock signal with the opposite phase given to another MOS transistor, and the drains are connected to produce the well voltage in a form of full wave rectification of the two level shift clock signals. COPYRIGHT: (C)2008,JPO&INPIT
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