发明名称 Wafer level bumping process
摘要 A bumping process mainly comprises the following steps. Initially, a wafer having a plurality of bonding pads and a passivation layer with passivation openings exposing the bonding pads is provided. Next, a first dielectric layer with first openings and second openings is disposed on the wafer. The first openings and second openings expose the bonding pads and the portions of the passivation layer respectively. Afterwards, a patterned first electrically conductive layer is formed over the first dielectric layer and the bonding pads. Then a second dielectric layer is formed over the first dielectric layer and the patterned first electrically conductive layer and exposes the patterned first conductive layer through the second openings to form a plurality of bump pads wherein the bump pads are electrically connected to bonding pads. Next, a second electrically conductive layer is formed over the second dielectric layer and the bump pads. Then, a plurality of bumps are formed on the portions of the second electrically conductive layer covering the bump pads. Finally, the bumps are reflowed and the portions of the second electrically conductive layer covered by the reflowed bumps are remained to form a patterned second electrically conductive layer.
申请公布号 US7223683(B2) 申请公布日期 2007.05.29
申请号 US20040876582 申请日期 2004.06.28
申请人 ADVANCED SEMICONDUCTOR ENGINEERING, INC. 发明人 LIN CHIAN-CHI
分类号 H01L21/44;H01L21/60;H01L23/485 主分类号 H01L21/44
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