| 摘要 |
Disclosed is a memory device having repeaters capable of preventing an expected signal delay and a signal distortion caused by a long transmission length of a long address signal and a long control signal. The memory device comprises: a plurality of banks; an address pad; an address driver for transmitting an address signal, which is inputted through the address pad, into each of the banks through address signal lines; a control pad; a control driver for transmitting a control signal, which is inputted through the control pad, into each of the banks through control signal lines; and repeaters arranged on the address signal lines and/or the control signal lines.
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