发明名称 FLOOR PLAN GENERATING METHOD, FLOOR PLAN GENERATING DEVICE AND FLOOR PLAN GENERATING PROGRAM FOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a floor plan generating method, floor plan generating device and floor plan generating program capable of ensuring a wiring area according to wiring congestion degree and shortening the period required for LSI design. SOLUTION: A floor plan area is divided into small sections, and the wiring congestion degree within each small section is estimated. Further, the shape of blocks is deformed according to the calculated wiring congestion degree so as not to overlap each other, and the wiring area according to the wiring congestion degree is ensured by this deformation of block shape. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003288380(A) 申请公布日期 2003.10.10
申请号 JP20020093167 申请日期 2002.03.28
申请人 FUJITSU LTD 发明人 YOKOMARU TOSHIHIKO
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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