| 摘要 |
PURPOSE: To reduce a peak current and coupling noise between adjacent data lines and to speed up serial reading by operating plural sense amplifiers time- dividely and alternately conducting the reading of odd lines and even lines. CONSTITUTION: Even data lines DL0, DL2 and odd data lines DL1, DL3 are connected to respective sense amplifiers(SAs) by switching respective transistors(TRs) MOSFETs by respective select signals F0, F1. Output signals from the SAs are outputted by select signals Y0 to Y3 through an YG gate. Since data lines are divided into two parts and the reading of memory cells is time- dividedly conducted, a read signal can be inputted simultaneously with its output and a peak current can be time-dividedly reduced. Since signals are not simultaneously applied to adjacent data lines on the memory mat side and coupling noise is removed, the high integration of memory arrays can be attained.
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