| 摘要 |
In a dynamic random access memory unit, a parity check logic circuit includes a parity signal generating circuit which generates a parity signal for each signal group transmitted on the input/output data bus. For a sequence of data groups on the data bus, a parity signal for each data group is generated, the parity signal combined with a parity signal generated for the previous data group or data groups. For a read operations, a parity signal is generated for each of sequence of retrieved data groups and combined with the parity signal(s) of the previous data groups of the sequence. The resulting parity signal is compared with the parity signal associated with the data group sequence and stored in the memory unit to generate a flag signal when the parity signals are not identical. For a write operation, the resulting parity signal for all the data groups is stored in memory unit at a location associated with the sequence of data groups. For a read-modify-write signal, the parity signal generated for each retrieved data signal is compared with the generated parity signal to be written into the memory location. When the signals do not match, the combined parity signal in the memory unit associated with the sequence including the retrieved and stored signal is changed to the opposite logic state. |
