| 摘要 |
PROBLEM TO BE SOLVED: To shorten the test time in the diagnosis of the cache memory. SOLUTION: An expected value A for a test is written in a memory 30, and read from a central processor 10 in cache enable mode and written in a cache memory 20, and this expected value is matched against source data on the expected value A. Then only the data in the cache memory 20 are rewritten with an expected value B, the forcible mishit mode of the cache is utilized to access the expected value A by the central processor, and the expected value A in the memory 20 and the expected value B in the cache memory 30 are exchanged. In cache disable mode, the central processor 10 accesses the expected value B to read its data out, which is matched against source data on the expected value B. When the memory 30 is accessed for the rewriting of the cache memory 20, addresses corresponding to head addresses by the lines of the cache memory 20 are accessed. Characteristics of the cache memory 20 allows all the data of the respective lines to be rewritten by the specification of the head addresses, so the access time is shortened. |
