AUTOMATIC DESIGNING METHOD FOR LOGIC CIRCUIT,申请号JP19950250467-传众专利搜索

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发明名称	AUTOMATIC DESIGNING METHOD FOR LOGIC CIRCUIT
摘要
申请公布号	JPH0991321(A)	申请公布日期	1997.04.04
申请号	JP19950250467	申请日期	1995.09.28
申请人	FUJITSU LTD	发明人	MATSUNAGA YUSUKE
分类号	G06F17/50;(IPC1-7):G06F17/50	主分类号	G06F17/50
代理机构		代理人
主权项
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