发明名称 NONVOLATILE MEMORY HAVING LOW FREQUENCY DETECTION CIRCUIT
摘要 <p>PURPOSE: To switch the boosting clock for a booster circuit between inner and outer clocks by a constitution wherein a nonvolatile memory incorporates a switch circuit including a low frequency detection circuit for permitting page writing at any write timing of CPU. CONSTITUTION: When a high frequency clock is generated from an external clock generation circuit 17 in order to determine the write timing of an EEPROM 11 for a CPU 6, the switching terminals of switches 121 , 122 in a switch circuit 12 are turned to side A so that the boosting clock for a booster circuit 14 is fed by the external clock and an internal clock generation circuit 13 is stopped. When the frequency of external clock lowers below a predetermined value, it is detected by a low frequency detection circuit 123 and the switching terminals of switches 121 , 122 are turned to side B so that the internal clock generation circuit 13 begins to oscillate the internal clock and the boosting clock for the booster circuit 14 is fed from the internal clock generation circuit 13.</p>
申请公布号 JPH08273384(A) 申请公布日期 1996.10.18
申请号 JP19950074057 申请日期 1995.03.30
申请人 TOSHIBA CORP 发明人 TAMURA KIYOSHI
分类号 G11C17/00;G11C16/06;(IPC1-7):G11C16/06 主分类号 G11C17/00
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