发明名称 |
Semiconductor memory unit |
摘要 |
A semiconductor memory unit that includes a regular memory cell array and a redundant column which utilize common rows for actuating regular memory cells when defective memory cells are detected. A first access device designates a column in the regular memory cell array which corresponds to a externally designated column address. A second access device designates a redundant column which corresponds to the externally designated column address. When the regular memory cell array contains defective memory cells and the column addresses of their cells coincide with the externally designated column address, a validating device validates the access to the redundant column by means of the second access device. When the regular memory cell array contains defective memory cells having column addresses other than that designated externally, the validating device validates the access to the column in the regular memory cell array by means of the first access device.
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申请公布号 |
US5452252(A) |
申请公布日期 |
1995.09.19 |
申请号 |
US19930136537 |
申请日期 |
1993.10.14 |
申请人 |
SANYO ELECTRIC CO., LTD. |
发明人 |
WADA, ATSUSHI;TAKANO, YOH |
分类号 |
G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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