发明名称 BIT MULTIPLEXING SYSTEM
摘要 PURPOSE:To prevent the phases of the signals of respective channels from being deviated after multiple separation on the reception side by respectively delaying a signal corresponding to the channel of a signal at the head position and a signal following to this signal for one bit among plural signals outputted from a serial/parallel converting means. CONSTITUTION:Based on detected channel identification information, a delay control means 9 recognizes a channel CH1 of the signal at the head position among the plural signals outputted from a serial/parallel converting means 4. While controlling a selective delay means 6, the signal corresponding to the channel CH1 at the head position and the signal following to this signal are respectively delayed for one bit among the plural signals outputted from the serial/parallel converting means 4. Thus, in the case of transmitting the digital signals of plural channels after multiplexing the bits by serial/parallel conversion, the phases of the signals of the respective channels can be prevented from being deviated after multiple separation on the reception side.
申请公布号 JPH04127734(A) 申请公布日期 1992.04.28
申请号 JP19900247453 申请日期 1990.09.19
申请人 FUJITSU LTD 发明人 IMAJI TERUTAKE;YAMATO SEIICHI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
代理机构 代理人
主权项
地址