| 摘要 |
PURPOSE:To improve the throughput of the arithmetic operation by providing a means charging a parasitic capacitance of a logic circuit network and discharging a wire capacitance of an output signal terminal independently to apply precharging. CONSTITUTION:In bringing a clock signal to a low level, precharge is started. In this case, FETs2, 4 are turned on and an FET3 is turned off, a parasitic capacitance 10 through the FET2 and a parasitic capacitor 11 through the FET4 are charged respectively and the potential of nodes 13, 14 rises. But a part or all of data signal input terminals 8 are at a high level and a logic circuit network 1 is in the conductive state, then the potential rise of the node 13 is delayed until the input terminal go to a low level and the logic circuit network is nonconductive. On the other hand, the potential of the node 14 rises independently of the state of the logic circuit network 1 because the FET3 is turned off, the wire capacitance 12 is discharged resulting from the turned-off FET5 and the turned-on FET6, the potential at an output terminal 9 is decreased to a low level and the precharge is finished.
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