| 摘要 |
PURPOSE:To reduce the load of a CPU by providing a termination detection circuit counting and detecting a bit string representing the absence of reception signal data transmission and applying DMA transfer to asynchronous serial reception data to a memory. CONSTITUTION:A communication control LSI1 receives asynchronizing reception data from a data terminal equipment and the data is subjected to DMA transfer to a memory 4 by the control of a DMA controller 7 for each character. When the reception packet is finished, the reception signal goes to a high state. The termination detection circuit 6 detects the high state, counts the reception clock during the said high state and when the count reaches a preset number, an interruption signal is generated for an interruption controller 3. Since hardware detects the end of packet and generates the interruption signal in this way, it is not required to transfer a data through a CPU 2, the DAM transfer is used and the load of the CPU 2 is relieved.
|
