| 摘要 |
PURPOSE:To apply the titled circuit for high speed intra-station transmission by obtaining the delay quantity by a counter and comparing the result with an address from an address counter controlling a delay memory thereby eliminating the need for the adjustment of delay even with a small circuit scale. CONSTITUTION:A flip-flop 11 is inverted at the period of an initializing pulse 10, that is, at each required delay time, and every time the flipflop 11 is inverted, the operating mode of a memory 9 and the selection mode of a selector 12 are subjected to switching control. The selector 12 outputs selectively a read data from the memory 9 in the read mode. Thus, in the memories 9 acting like a double buffer, while a data is read from one memory, an input data 4 is written in the same address in the other memory and the read data is obtained from the selector 12. Since the same operation is repeated sequentially by the initializing pulse 10 in this way, the input data 4 delayed as desired is obtained from the selector 12 simply. |
