Programmable asynchronous register initialization circuit

摘要

A circuit constructed in accordance with this invention includes means for asynchronously forcing a flip-flop (70) or a register to a programmable logical state in response to an initialization input signal ( &upbar& I). In one embodiment, a D-type flip-flop (70) is provided having data input terminal (71), a clock input terminal (77), a data output terminal (103), an initialization input terminal (41), and a programming input terminal (11). When an initialization input signal &upbar& I is received, a predefined output signal is immediately placed on the data output terminal (103). The predefined output signal is defined by the status of a fuse (13), which is opened, if desired, via the programming input terminal (11). When an initialization input signal is not received, the flip-flop (70) operates as a normal D-type flip-flop.