| 摘要 |
<p>A buffer storage system for a pipeline processor, set up with at least an operand access buffer storage and an instruction fetch buffer storage. The buffer storages cooperate with store address registers and store data registers, to assume a store-through method between the buffer storages and a main storage. A feedback means is mounted between the buffer registers and the store address/data registers. This feedback means is activated during an operand store operation to apply an operand store address and an operand store data, from the store address and store data registers, to the instruction fetch buffer register for effecting coincidence in data among the storages.</p> |
