| 摘要 |
<p>PURPOSE:To obtain the unified signal from anywhere in each key region, by applying positive voltage signal to one conductor group in two sets of conductor groups or a plurality of conductors, applying negative voltage signal to all other conductors, and applying positive voltage signal to each conductor of other conductor group. CONSTITUTION:When the clock generation circuit 10 outputs clock pulse, the address counter 11 counts it. Within the time of first one pulse, + V voltage pulse is outputted to the lower conductor Y1 and -voltage pulse is outputted to other lower layer conductors Y2-Y4. On the other hand, the X drive circuit 9 inputs the X selection signal of low level 0 from the selection circuit 12 and the +V voltage pulse is fed to the upper layer conductors X1-X4. At the next pulse period, the Y decoder driver 20 of the Y drive circuit 9 selects the next lower layer conductor Y2 and feeds +V voltage.</p> |
