发明名称 Method for making vertical interconnections through structured layers
摘要 <p>#CMT# #/CMT# The method involves defining a surface contact region of a surface connection layer over a surface (2') of a stack and a contact region (41) embedded in the stack from an embedded connection layer (4) of a substrate (1) of the stack, where a region (61) devoid of material is positioned between the substrate and another substrate (2). An interconnecting well (82), which passes via the latter substrate and extends between the contact regions and passes via the devoid region, is produced by plasma etching from the stack surface. An insulating layer (5) covering the embedded layer is produced. #CMT#USE : #/CMT# Method for producing an interconnecting well to form a conductive pathway between two connection layers of a component such as complex microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS) device. #CMT#ADVANTAGE : #/CMT# The method enables producing, in a single stage, two sections of the interconnection or pathway, thus simplifying the sequence of stages of manufacture of complex devices while economizing approximately 25 percent of the number of the stages, and hence reducing the manufacturing costs of the complex devices. #CMT#DESCRIPTION OF DRAWINGS : #/CMT# The drawing shows a sectional view illustrating simultaneous etching of two interconnecting wells by plasma etching. 1, 2 : Substrate 2' : Surface of stack 4 : Embedded connection layer 5 : Insulating layer 41 : Embedded contact region 61 : Region devoid of material 82 : Interconnecting well.</p>
申请公布号 EP2498287(B1) 申请公布日期 2014.11.12
申请号 EP20120158256 申请日期 2012.03.06
申请人 COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIESALTERNATIVES 发明人 BERTHELOT, AUDREY;POLIZZI, JEAN-PHILIPPE
分类号 H01L21/768;B81C1/00;H01L23/48 主分类号 H01L21/768
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