发明名称 |
Single-event upset immune static random access memory cell circuit, system, and method |
摘要 |
A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell.
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申请公布号 |
US7876602(B2) |
申请公布日期 |
2011.01.25 |
申请号 |
US20080141900 |
申请日期 |
2008.06.18 |
申请人 |
BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. |
发明人 |
LAWRENCE REED K.;HADDAD NADIM F. |
分类号 |
G11C11/00 |
主分类号 |
G11C11/00 |
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