发明名称 Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers
摘要 A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in the local block, and can also pass through samples output by an upstream local block. The selected samples from local blocks are sent to a central on-chip logic analyzer that compares the samples to a maskable trigger value. When the trigger value is matched, a trigger state machine advances, and samples are stored into a central capture buffer. A user debugging the chip can later read out the central capture buffer at a slower speed. Thousands of internal nodes from local blocks can be selected for sampling, triggering, and debugging. Local blocks include valid bits in 64-bit-wide samples. Only valid samples are written to the capture buffer.
申请公布号 US7332929(B1) 申请公布日期 2008.02.19
申请号 US20060308048 申请日期 2006.03.03
申请人 AZUL SYSTEMS, INC. 发明人 NORMOYLE KEVIN B.;REDDY SREENIVAS;PHILLIPS JOHN
分类号 G06F11/00;G01R31/28 主分类号 G06F11/00
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