| 摘要 |
<p>A delay circuit composed of taps (TAP0 to TAPn) for imparting a unit delay time (tau) interconnected in series to form multiple stages. Each tap has the same structure. An object signal is inputted into a signal input terminal (I1). The inter-stage connection terminal (I2) of each tap is connected to the output terminal of the preceding-stage tap. The output terminal (O) is connected to the inter-stage connection terminal of the next-stage tap. The signal input terminal and the inter-stage connection terminal are connected to the input terminal of one of NAND gates (1, 2). A tap selection signal is inputted into the input terminal of the other NAND gate. The output terminal is connected to a NAND gate (3). Either of the NAND gates (1, 2) functions as a logical inversion gate according to the tap selection signal, thereby enabling signal propagation. The level of the output signal of the other NAND gate is fixed to a high level, and the NAND gate (3) also functions as a logical inversion gate. Through the NAND gates (1, 3), the object signal is propagated; and through the NAND gate (2, 3), the preceding-stage signal is propagated. If the structures of the NAND gates (1, 2) are the same, the unit delay times (tau) can be made to agree with each other with high accuracy.</p> |
