FLIP-FLOP CIRCUIT AND SHIFT REGISTER

摘要

PROBLEM TO BE SOLVED: To reduce a layout area, and to reduce power consumption in the transition of a clock signal by reducing the number of MOS transistors of a flip flop circuit.

SOLUTION: A P channel MOS transistor 11 and an N channel MOS transistor 12 respectively connected to an internal normal rotation clock node ck and an internal inversion clock node ckb are shared by a try state inverter 1 included in a master latch and a try state inverter 5 included in a slave latch.

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