发明名称 |
SEMICONDUCTOR DEVICE INCLUDING BUILT-IN REDUNDANCY ANALYSIS CIRCUIT FOR SIMULTANEOUSLY TESTING AND ANALYZING FAILURE OF A PLURALITY OF MEMORIES AND METHOD FOR ANALYZING THE FAILURE OF THE PLURALITY OF MEMORIES |
摘要 |
A semiconductor device including a built-in redundancy analysis (BIRA) circuit for simultaneously testing and analyzing failures of a plurality of memories, and a failure analyzing method, includes a plurality of memory blocks, a plurality of built-in redundancy analysis units for outputting a group of failure repairing information signals by testing and analyzing a corresponding memory block among the plurality of memory blocks in response to common driving signals and each of independent selection signals, and a controller for generating the common driving signals and the respective independent selection signals in response to a plurality of externally applied control signals and sequentially receiving and sequentially outputting the group of failure repairing information signals generated from the respective built-in redundancy analysis units. According to the semiconductor device and the failure analyzing method, it is possible to reduce the test time and expense since a plurality of memories having different sizes can be simultaneously tested and analyzed.
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申请公布号 |
US6603691(B2) |
申请公布日期 |
2003.08.05 |
申请号 |
US20010981456 |
申请日期 |
2001.10.17 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
YOO YOUNG-DOO;JUN HONG-SHIN |
分类号 |
G11C29/44;(IPC1-7):G11C7/00 |
主分类号 |
G11C29/44 |
代理机构 |
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地址 |
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