发明名称 Viterbi decoder with pipelined ACS circuits
摘要 In a Viterbi decoder, a sequence of branch metrics is derived from a received convolutional codeword sequence. The branch metric sequence is divided and supplied to add/compare/select (ACS) circuits where the divided branch metric sequences added to previous path metrics. Path metric sequences of maximum likelihood paths are determined by the ACS circuits and indicators identifying the maximum likelihood paths are produced. A pipelining circuit is provided for reordering, or pipelining state metrics of the path metrics of the maximum likelihood paths and supplying the pipelined state metrics to the ACS circuits. The indicators from the ACS circuits are used to recover an original bit sequence.
申请公布号 US6259749(B1) 申请公布日期 2001.07.10
申请号 US19970939911 申请日期 1997.09.29
申请人 NEC CORPORATION 发明人 ANDOH TAKESHI
分类号 G06F17/10;H03M13/23;H03M13/41;(IPC1-7):H03D1/00 主分类号 G06F17/10
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