| 摘要 |
The reading device comprises a differential amplifier (2) with inputs (MTX, REF) each connected to the output (SR, SD) of respective current-voltage converter (CIVD, CIVR), whose inputs are connected to the selected bit and reference bit lines (Bl, Blref), respectively, where each converter can precharge the associated bit line to a first precharge voltage (Vbias 1) in the precharge phase, a read current generator (GEN) for establishing the data at device output in the following estimation phase, circuits (PCHMTX, PCHREF) for precharging the inputs of differential amplifier to a second precharge voltage (Vbias 2), which is between the first precharge voltage (Vbias 1) and the supply voltage (Vdd), and a circuit (50) in the control block for detecting the end of precharge phase in order to stop the precharge and activate the read current generator (GEN) for the estimation phase. The read current generator (GEN) receives a control signal (MIR) for deactivation in the precharge phase and activation in the estimation phase, where the signal is provided by a control block (5) comprising the circuit (50) for detecting the voltage drop at the input (ER) of converter, and a logic circuit (51). The second precharge voltage (Vbias 2) is about 1.5 V. The device in detailed embodiment also comprises means for equalization of internal nodes controlled by the signal (MIR), and the means are in the form of passgates. Each converter (CIVD, CIVR) comprises a transistor (T1) connected between input and output of converter, and an inverter (I1) connected between the input of converter and the gate of transistor. The circuit (50) comprises two inverters, one dimensioned so to detect the voltage drop before the other associated with the reference bit line. An integrated circuit memory comprises a reading device according to the invention.
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