| 摘要 |
Efficient use of a cache memory in a computer system is achieved, the system comprising a processor (12), a local bus comprising local address (110) and local data buses (111) coupled to the processor, a cache memory (16) coupled to the local bus, a bus interface (20) coupled to the local bus for coupling the processor to a main memory via an external bus (141, 142) and a transparent write cache policy (TWCP) controller (14) functionally coupled between the processor and bus interface. The TWCP controller looks for a data write operation initiated by the processor, and signals the processor that the data write is complete before actual completion, to free the processor to engage in one or more subsequent operations that do not require the external bus. The TWCP controller causes the bus interface to complete the data write to main memory in parallel with the one or more subsequent operations.
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