发明名称 Output buffer circuit with logic gate control circuitry
摘要 The present invention has the object of improving operation speed and operation margin for a GTL driver. An output buffer circuit is of push-pull construction using N-channel MOS transistors MN11 and MN12. An output signal is fed back to pull-up transistor MN11 by way of NOR circuit NOR1, and a low-amplitude, high-speed signal waveform is outputted. The output of this output buffer circuit is inputted to a differential input circuit of another semiconductor integrated circuit. The reference input of the differential input circuit is connected to a reference voltage supply, and the input of the differential input circuit is terminated to the reference voltage supply by terminating resistance. By means of this configuration, the input amplitude of the differential input circuit oscillates with respect to the reference voltage without being affected by the power supply voltage of the output buffer circuit, the power supply voltage of the differential input circuit, or power-supply fluctuations of the reference voltage, thereby broadening the margin against noise.
申请公布号 US5661415(A) 申请公布日期 1997.08.26
申请号 US19960608318 申请日期 1996.02.28
申请人 NEC CORPORATION 发明人 AOKI, YASUSHI;KATAYAMA, ATSUSHI
分类号 H03K19/0175;H03K19/00;H03K19/017;H04B3/18;(IPC1-7):H03K19/017 主分类号 H03K19/0175
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