发明名称 |
Multi-way set associative cache system in which the number of lines per set differs and loading depends on access frequency |
摘要 |
A set associative cache system in a computer system having a lower memory is provided with a plurality of cache memory sets. A cache data memory contains a plurality of cache lines to store data in units of blocks corresponding to data stored in the lower memory. A cache tag memory stores lower memory addresses for data stored in the cache lines. The plurality of cache memory sets have different numbers of cache lines. A read/write section reads out data stored in the lower memory into the plurality of cache lines and writing data in the plurality of cache lines back to the lower memory.
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申请公布号 |
US5651135(A) |
申请公布日期 |
1997.07.22 |
申请号 |
US19950413010 |
申请日期 |
1995.03.29 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
HATAKEYAMA, TETSUO |
分类号 |
G06F12/08;G06F12/12;(IPC1-7):G06F12/02 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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