发明名称 CLOCK TRANSFER CIRCUIT
摘要 PURPOSE:To detect a fault by the scan path method by allowing a digital transmitter to use an internal clock so as to latch parallel data outputted by itself when a switching control pulse is not active. CONSTITUTION:An S/P conversion section 1 fetches serial data inputted synchronously with a transmission clock SCLK and outputs parallel data in a timing of an S/P conversion pulse SPP synchronously with the transmission clock. An extension circuit 3 generates an extension pulse LP resulting from extending the pulse SPP by a bit length over a period of an internal clock. A differentiation circuit 4 differentiates a trailing edge of the pulse LP synchronously with the internal clock to generate a switching control pulse CTP. A clock transfer section 2 latches the parallel data from the conversion section 1 when the pulse CTP is active and parallel data outputted by itself in other cases based on the internal clock ICLK and the latched data are outputted.
申请公布号 JPH05316086(A) 申请公布日期 1993.11.26
申请号 JP19920117852 申请日期 1992.05.12
申请人 FUJITSU LTD 发明人 SUGAWARA AKIRA;IKUTA KOJI;OGATA HIROKI
分类号 H04L7/00 主分类号 H04L7/00
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