| 摘要 |
<p>PURPOSE:To set the operating data signal speed automatically without any adjustment operation by providing a clock signal generator for a frequency being the integer multiple of the data signal speed, a shift register storing a received data synchronously with a clock and a signal speed identification means. CONSTITUTION:After a reset signal (r) is inputted at first to each element, a data (d) is inputted to an FF 2 via an inverter 1 and a counter circuit CNT 3 starts the count of a clock ck' by using a start signal (g) and a clock ck whose object data signal speed is 600bps and 300bps resulting from the frequency division of the clock ck' from a terminal Q3. A shift register 4 stores a data (d) synchronously with the clock ck and sets the logical values of signals q0-q11 at the output terminals q0-q11 to a logical value of each bit stored in each stage. A detection circuit 51 extracts the signals q0-q5 and inverts them, brings the level of the signal a1 to '1' with a prescribed AND and the speed of the signal (d) is 600Hz and a detection circuit 52 detects a frequency 300Hz when the level of the detection signal a2 is logic '0' FFs 61, 62 latch identification signals b1, b2 and switch the communication speed automatically depending on the logical value of the signals b1, b2.</p> |
