| 摘要 |
<p>A microprocessor (l00) and a peripheral equipment communicate data through a bus (l40). If an error occurs during the communication, the microprocessor starts the next bus cycle and commands retry of the data communication. If a predetermined number of times of retry fail, or if an address signal corresponds to access to an unmounted area of the peripheral equipment or an area of an I/O equipment, the microprocessor inhibits the retry.</p> |
