Byte wide EEPROM with individual write circuits and write prevention means

摘要

An array arrangement for EEPROMS in which each memory cell has two transistors. Selection is simplified whereby in selecting a cell all of the cells in the selected row are connected to one terminal of the writing circuit and all the cells in the selected column are connected to the other terminal. This selection process prevents any cell from being written into except the cell at the intersection of the selected row and the selected column.