| 摘要 |
PURPOSE:To output pulses of M-fold frequency without varying the duty ratio of pulses of optional frequency which has an optional duty ratio. CONSTITUTION:A master clock signal (a) is supplied to a counting part 106 which counts the number N1 of pulses of the master clock indicating the continuance of the ''Low'' level of an input pulse signal to calculate N1'=N1/M (M: frequency multiplication rate). The counting part 105 goes up to the logical ''Low'' level at the rise of the input pulse signal (j) to outputs a pulse signal (f) which goes down to the logical ''Low'' level when counting up to Nphi'. The counting part 106 rises at the timing of the rise of the pulse signal (f) and outputs a pulse signal (g) which falls when the counting part counts the master clock signal (a) up to N1'=N1/M. The counting part 107 rises at the timing of the fall of the pulse signal (g) and outputs a pulse signal (i) which falls when the counting part counts the master clock signal (a) up to N0'=N0/M. A gate part 108 ORs the pulse signal (f) with the pulse signal (i) and outputs an output pulse signal (h). |
