发明名称 BUS CONTROL SYSTEM
摘要 PURPOSE:To omit registers corresponding to each control part by providing a control memory which stores the transfer control information and the transfer result information and a control means that performs the direct transfer of information between said control memory and a memory in each control part. CONSTITUTION:A detection part DET403 of a bus control part 4 detects that both host and local control parts 1 and 2 are ready for transmission and reception and then starts a transfer control part FCL404. Thus the transfer control information HCCW and LCCW are extracted out of memories 11 and 21 of both control parts 1 and 2. These information are stored directly to a memory 405 in the part 4. Based on these information, the memory data is transferred directly between memories 11 and 21. The transfer results HCSW and LCSW are also transferred directly to memories 11 and 21 from the memory 405.
申请公布号 JPS615364(A) 申请公布日期 1986.01.11
申请号 JP19840125779 申请日期 1984.06.19
申请人 FUJITSU KK 发明人 SHIYOUJI MASAHIKO;CHINO MAMORU;TAKANO RIYOUJI
分类号 G06F13/38;G06F13/28;G06F15/17;(IPC1-7):G06F13/28 主分类号 G06F13/38
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