| 摘要 |
PURPOSE:To omit a latch circuit and to simplify a circuit by outputting a timing signal to a memory in accordance with a write or read designating signal and generating an acknowledge signal designation the end of writing or reading in/ from the memory. CONSTITUTION:Receiving a write designating WT or a read designating signal RD, a bus timing circuit 3 outputs a MEMREQ signal. Receiving the MEMREQ signal, a memory timing circuit 7 outputs a timing signal to an RAM2. Consequently, the RAM2 writes the data of an external bus 1 through an internal bus 8 or reads out the data of the RAM2 to the external bus 1 through the internal bus 8. On the other hand, an FF9 outputs an acknowledge signal ACK designating the end of data writing or reading and a signal stopping the access cycle of the memory. Thus, the latch circuit can be omitted and the circuit can be simplified. |
