发明名称 |
FERROELECTRIC MEMORY DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To realize improvement in the integration of a ferroelectric memory device. SOLUTION: The ferroelectric memory devices have the first capacitor group and the second capacitor group composed of a plurality of ferroelectric capacitors arranged in the first direction respectively. The first bit line group consists of a plurality of bit lines BL0, BL2, BL4 and BL6 extending in the second direction orthogonal to the first direction. The second bit line group is composed of a plurality of bit lines BL1, BL3, BL5 and BL7. Each ferroelectric capacitor constituting the first capacitor group is connected to each bit line configuring the first bit line group respectively through corresponding memory cell transistors. Each ferroelectric capacitor organizing the second capacitor group is connected to each bit line constructing the second bit line group respectively through corresponding memory cell transistors.
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申请公布号 |
JP2003158245(A) |
申请公布日期 |
2003.05.30 |
申请号 |
JP20010358946 |
申请日期 |
2001.11.26 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
HIRANO HIROSHIGE;YAMAOKA KUNISATO |
分类号 |
H01L27/105;H01L21/8246;(IPC1-7):H01L27/105 |
主分类号 |
H01L27/105 |
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