| 摘要 |
<p>An integrated circuit manufacturing process and the product formed thereby for an interpoly dielectric used in floting gate memory devices such as Flash EPROM provides for scaling down in dielectric thickness without lowering yield. The use of a cluster deposition system for the ONO layers of the interpoly dielectric lowers the amount of carbon-based residue on the dielectric layers and lowers the leakage current.</p> |
