CONTROL CIRCUIT FOR COLUMN SELECTION SIGNAL

摘要

PROBLEM TO BE SOLVED: To secure the enable time and suppress error by changing the delay path of enable signals and the width of column selection control pulse according to the theory of writing signal. SOLUTION: An enable signalϕCPE is delayed by a first delay circuit of inverters 42, 44 and subjected to theoretical calculation in a NOR gate 50. It is outputted through an inverter 52 to a NAND gate 66, the inverters 54, 56 of a second delay circuit and an AND gate 58 of the second delay selection circuit. On the other, hand, the first delay selection circuit of an AND gate 46 is shorter in delay time and faster in response speed than the first delay circuit, and theoretically calculates theϕCPE when the writing signalϕWR is low. Likewise the second delay selection circuit theoretically calculates the output of the inverter 52 whenϕWR is high. Next, the NOR gate 62 theoretically calculates and outputs a column selection control signalϕCP through inverters 64, 65, a NAND gate 66 and inverters 68, 70. By this, the enable time of the column selection signal is secured and error is suppressed.