发明名称 BIT SYNCHRONIZING DEVICE
摘要 PURPOSE:To shorten pull-in time on synchronization by storing by deciding in which interval out of the intervals where one period of a reproducing clock is divided into (m) intervals a timing signal occurs. CONSTITUTION:A decoder 7 detects in which interval out of the intervals where one period of the reproducing clock is divided into the (m) intervals the timing signal exists at present by using a variable frequency divider 5 and a frequency divider 6, and count up by a counter (one of counters 9-1, 9-2,..., 9-m) taking charge of the present interval is enabled. An enabled counter counts the timing signal sequentially. The counter (one of counters 9-1, 9-2,..., 9-m) whose value arrives at (n) times issues a reset request to a reset timing generator 8. The reset timing generator 8 resets the variable frequency divider 5 and the frequency divider 6 so as to initialize the phase of the reproducing clock at the interval from where the reset request is issued.
申请公布号 JPH05227146(A) 申请公布日期 1993.09.03
申请号 JP19920026287 申请日期 1992.02.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IGAWA KEIICHI
分类号 H04L7/033;H04L7/10 主分类号 H04L7/033
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