| 摘要 |
<p>PURPOSE:To prevent the error of transmitting data due to a frequency abnormality by detecting that the time difference between a buffer input timing and a buffer output timing slips off from a prescribed allowance and providing a means to output an abnormal signal. CONSTITUTION:When prescribed number of bits of receiving data is set to a receiving shift register part 2, the data of the prescribed bit are inputted to a buffer part 3. When the data of a prescribed bit synchronized to a transmitting clock signal and set into a transmitting shift register part 4 are completed to serially transmit, the data of the next prescribed bit are inputted from a buffer part 3 to a transmitting shift register part 4 and in succession, transmitted serially. At this time, a timing abnormality detecting circuit 6 detects a buffer input timing in which the receiving data are inputted from the receiving shift register part 2 to the buffer part 3, and a buffer output timing in which the receiving data are inputted from the buffer part 3 to the transmitting shift register part 4. When it is detected that the time difference in the timing slips off from a prescribed allowance, an abnormal signal is outputted.</p> |
