| 摘要 |
<p>A sample-and-hold circuit is provided wherein an input signal is fed via a first gate element (7) to one end of a first capacitor (12) whose other end is grounded alternatingly, the one end of the first capacitor (12) being connected via a second capacitor (11) to a gate (or base) of a source (or emittor) follower transistor (9) to obtain an output from the source (or emitter) of the transistor (9) which is connected via a second gate element (10) to one end of the first capacitor (12). while the gate (or base) of the transistor (9) is connected via a third gate element (8) to a DC voltage supply having a predetermined voltage value, and the second and third gate elements (10, 8) are turned on during a first period of the input signal so that a voltage corresponding to the gate-source (or base-emitter) offset voltage of the transistor (9) is stored in the second capacitor (11), while the first gate element (7) is turned on during a second period of the input signal to produce an output signal equivalent in level to the input signal.</p> |
