发明名称 Cache architecture
摘要 A cache controller for a processing system, the cache controller being capable of providing an interface between a data requester and a plurality of memories including a first memory, a second memory and a cache memory, the cache controller being configured to, in response to receiving a request for data at a specified address in a specified memory, perform the steps of: determining whether either (a) a data field in the cache memory that corresponds to the specified address has been populated from the specified memory or (b) the specified memory is the first memory and the data field corresponding to the specified address in the cache memory has been populated from the second memory; and if that determination is positive, responding to the request by providing the content of the data field in the cache memory corresponding to the specified address.
申请公布号 GB2534014(B) 申请公布日期 2017.01.04
申请号 GB20150019887 申请日期 2014.08.06
申请人 Qualcomm Technologies International, Ltd. 发明人 Paul Hoayun
分类号 G06F12/06;G06F12/0875;G06F12/126 主分类号 G06F12/06
代理机构 代理人
主权项
地址