发明名称 MERGING INFRASTRUCTURE IN DEVELOPMENT ENVIRONMENT
摘要 PROBLEM TO BE SOLVED: To design circuits in a high-level graphical design environment without requiring HDL design knowledge. SOLUTION: A development environment includes a graphical design tool and structure agents. The graphical design tool allows a designer to design primary logic components of the circuit. The design tool generates modules, which express the primary logic components, using a hardware description language, and the modules include abstraction references for infrastructures of the circuit. The structure agents synthesize the modules to a netlist and merges them with infrastructure descriptions of the circuit. Infrastructures are generated in a development environment independent from the design tool. The structure agents include an adjuster to adjust the modules, and the adjustment of the modules includes that the abstraction references for the infrastructures are replaced with actual references to be used within the infrastructures. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005346710(A) 申请公布日期 2005.12.15
申请号 JP20050155204 申请日期 2005.05.27
申请人 AGILENT TECHNOL INC 发明人 HAMILTON ROBERT ANSON;JEFFERSON STANLEY TED;COVERSTONE RANDY ALLEN
分类号 G06F9/44;G06F9/455;G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F9/44
代理机构 代理人
主权项
地址