MULTI-FRAME SYNCHRONIZING CIRCUIT

摘要

PURPOSE:To ensure the detection of a multi-frame synchronizing signal and to minimize the discrimination of the establishment of synchronization in mistake by other than mentioned below signals by checking whether or not a series of plural bits included in a multi-frame synchronizing signals of a prescribed code pattern takes place in a prescribed order so as to detect the multi- frame synchronizing signal. CONSTITUTION:A serial bit string coming to an input terminal 1 is inputted sequentially to the input A of a shift register 4 and outputted in parallel from outputs Q1-Q7 sequentially. Read addresses A1-A7 of a ROM 21 are designated by the output and stored data 00-04 of the designated storage position are read to an input 30 of a selector 23 and inputs B0-B4 of a comparator 26. When the multi-frame synchronization is established, a selector 23 selects an input 32 from a register 25 by an output 42 of a protection circuit 12, an adder 24 adds '1' and inputs the results to the register 25. An output 38 of the register 25 is inputted to inputs A0-A3 of the comparator 26. The input A4 receives always logic 0. The comparator 26 compares both the inputs A0-A4 and B0-B4 and outputs the result of comparison to the protection circuit 12.