FERROELECTRIC MEMORY

摘要

PROBLEM TO BE SOLVED: To improve tension characteristics and a yield rate by preventing a reduction in the sense margin of a bit line arranged in the end of a memory cell array. SOLUTION: Dummy bit lines Dummy BL and Dummy/BL are arranged by setting a pitch equal to a pitch between bit lines in a memory cell array MCA outside a bit line BL0 arranged in the end of the memory cell array MCA. The Dummy BL and the Dummy/BL have wiring widths equal to bit lines in the memory cell array MCA. A memory cell block MCB is connected to the Dummy BL and the Dummy/BL. A sense amplifier circuit SA is connected to the dummy bit lines Dummy BL and Dummy/BL, while a data line DQ is not connected. COPYRIGHT: (C)2005,JPO&NCIPI