发明名称 |
Integrated scalar and vector processors with vector addressing by the scalar processor |
摘要 |
A vector processor is closely integrated with a scalar processor. The scalar processor provides virtual-to-physical memory translation for both scalar and vector operations. In vector operations, a block move operation preformed by the scalar processor is intercepted, the write command in the operation is converted to a read, and data resulting from a vector operation is returned to the address specified by the block move write command. Writing of the data may be masked by a prior vector operation. Prefetch queues and write queues are provided between main memory and the vector processor. A microinstruction interface is supported for the vector processor.
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申请公布号 |
US5123095(A) |
申请公布日期 |
1992.06.16 |
申请号 |
US19890297981 |
申请日期 |
1989.01.17 |
申请人 |
ERGO COMPUTING, INC. |
发明人 |
PAPADOPOULOS, GREGORY M.;CULLER, DAVID E.;PINKERTON, JAMES T. |
分类号 |
G06F9/315;G06F9/345;G06F9/38;G06F12/10;G06F15/78;G06F17/16 |
主分类号 |
G06F9/315 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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