发明名称 |
Memory access techniques utilizing a set-associative translation lookaside buffer |
摘要 |
A memory access technique, in accordance with one embodiment of the present invention, includes caching page size data for use in accessing a set-associative translation lookaside buffer (TLB). The technique utilizes a translation lookaside buffer data structure that includes a page size table and a translation lookaside buffer. Upon receipt of a memory access request a page size is looked-up in the page size table utilizing the page directory index in the virtual address. A set index is calculated utilizing the page size. A given set of entries is then looked-up in the translation lookaside buffer utilizing the set index. The virtual address is compared to each TLB entry in the given set. If the comparison results in a TLB hit, the physical address is received from the matching TLB entry. |
申请公布号 |
US8707011(B1) |
申请公布日期 |
2014.04.22 |
申请号 |
US20060588177 |
申请日期 |
2006.10.24 |
申请人 |
GLASCO DAVID B.;YUAN LINGFENG;NVIDIA CORPORATION |
发明人 |
GLASCO DAVID B.;YUAN LINGFENG |
分类号 |
G06F12/00;G06F13/00;G06F13/28 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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